Sinusoidal voltages can be generated in a single-phase or three-phase configuration through a power converter followed by a passive filter. In an open-loop system or a closed loop system controlling the RMS value, the output voltage experiences a distortion due to the filter inductance and the natural operation of the semiconductor devices. This particular distortion reduces the RMS of the output voltage and deteriorates the total harmonic distortion (THD) of the output voltage, often in excess of conventional standards.
An auxiliary power distribution system (APDS) is comprised of an inverter and a passive filter. Different filter topologies have been used to cancel the effects of the harmonics produced by the switching operation of the pulse width modulation (PWM) inverter. These filter topologies include e.g. single or multiple low-pass LC filters, combinations of low-pass LC filters and trap resonant filters. Typically these solutions start with an inductor at the inverter leg or have an equivalent inductive character at the fundamental frequency. This inductor is seeing the inverter pole voltage on one side and a sinusoidal voltage on the other side. The ripple of the current through insulated gate bipolar transistors (IGBTs) and the filter inductor is calculated from the voltage drop across the inductor.
Due to the real characteristics of the power semiconductor devices with finite delays and switching times, a time interval is introduced between the turn-off of an IGBT and the turn-on of the other IGBT on the same leg. This interval is called blanking time. Despite the advantages in protection of the power stage, the blanking time interval alters the effective value of each pulse depending on the current direction. Under positive current, the low-side diode turns on after the high-side IGBT turns off. The effective value of the voltage on the load is decreased by an interval equal to Vdc*tb/T, tb being the blanking time. In contrast, a negative current increases the pulse voltage by Vdc*tb/T. Finally, if the current crosses the zero axis, the pulse width is preserved within some limits, but the pulse is shifted. These limits depend on the actual size of the command or reference pulse.
This problem is well known in motor drive applications where the current is quasi-sinusoidal. Different compensation methods have been reported, based on pulse width feedback, fast current compensation, or open-loop voltage compensation. The simplest compensation adds a supplemental square-wave to the reference signal with a magnitude equal to the tb/T (for a unity reference) and phase synchronized with current direction. The amount of voltage error to be compensated does not depend on the amount of current but on the current direction.
A compensation for the voltage error due to the blanking time is difficult to implement in the case of an inverter-filter system due to the multiple crossings of the zero axis of the current. The compensation would consist of adding a voltage during the intervals of purely positive current and subtracting a voltage during the intervals with purely negative currents. There is no blanking time compensation required during the intervals when the current crosses the zero axis. The simplest implementation following this reasoning is based on a quasi-square waveform. Such a method is very similar to the blanking time compensation used in motor drives.
The conventional compensation for the blanking time applied to a system having zero current clamping distortion is based on determining the amount of compensation required. As previously explained the blanking time compensation for the distorted voltage waveform differs from the original ones by a quasi-square wave. The RMS value of the component on the fundamental frequency will be decreased by the corresponding RMS value of the fundamental component of the square wave corresponding to the blanking time. This simple compensation is close to the requirements for a RMS value of the output voltage within +/−5% of nominal but does not correct the THD of the output voltage. Moreover, it is very sensitive to the proper synchronization of the correction waveform to the output voltage. A slight angular error may produce a glitch in the voltage waveform. The difference between the results of this blanking compensation and the desired value of the output RMS voltage and THD are due to the zero-current clamping. Unfortunately, the inverter-filter case is more complex and the blanking time cannot be compensated alone without considering the zero current clamping.
Zero current clamping is an issue each time the current crosses zero, where the conduction changes from an IGBT device to the anti-parallel diode. If the inverter is switched at near zero current, the conducting device turns-off while the conduction of the other device is delayed. There is not enough energy in the load circuit to turn on the anti-parallel diode and there is no voltage before the IGBT is actually turned-on by the control. Even the turn-on of an IGBT at zero current takes place with a large turn-on time. At high switching frequencies, this affects the quality of the output voltage waveform. This current-dependent distortion is inherent to semiconductor devices and it is usually called zero current clamping This distortion is minimal within a motor drive system since there is only a zero crossing on each fundamental component of the current, but very important within an inverter-filter system.
In an inverter-filter assembly, the sinusoidal output voltage is created with low-pass filtering of a modulated train of voltage pulses. At any given pulse, the current through the inductor and the voltage across the capacitor within the filter are determined from their initial value and the width of the applied pulse. When a pulse is shorter than expected, the equivalent “volt*sec” product decreases and the value of the current at the end of the interval is smaller. If the initial value of the current on the following pulses is different than expected due to any physical characteristic of the circuit, the final and the average values for those pulses are modified. If the inductor current is different from the expected value due to circuit related issues, the voltage on the output capacitor is other than sinusoidal. The current distortion determines a “shoulder” of the output voltage and a reduction of the RMS value of the output voltage, also known as waveform flat-topping. The affected region will be shifted if the load power factor is not unity. The loss in voltage RMS is not the only negative effect of the waveform flat-topping. As mentioned, the THD of the output voltage is also altered and a strong third harmonic is introduced. This voltage error is not due to the effect of the blanking time alone since the current bounces around the zero axis during each sampling period and it never clearly defines the “one-direction current” interval. Even a zero blanking time would not produce the required 120 Vrms voltage. On the other hand the blanking time definitely has an influence on the zero current clamping. The larger the blanking time, the larger the zero current clamping interval.